BPM Microsystems to demonstrate the 2800ISP at the Houston SMTA Expo
HOUSTON — March 13, 2013 — BPM Microsystems announces that it will exhibit its award-winning 2800ISP parallel in-system device programmer at the Houston SMTA Expo, scheduled to take place March 14, 2013 at the Stafford Centre in Stafford, TX.
The new 2800ISP incorporates the company’s 8th Generation site technology utilizing its Vector Engine Co-Processor® into a custom-designed test fixture, allowing its customers to program flash architectures including eMMC, PCM and raw NAND, plus MCUs and other device technologies on-board after reflow. In 2012, the company added support for third party functional testing, such as boundary scan, with the capability to test up to 240 pins in addition to the 960 pins available for programming.
Ideal for medium- to high-volume production, the 2800ISP is configurable and can program up to 16 devices in parallel. Like all 8th Generation programmers, the 2800ISP with BPM’s Vector Engine Co-Processor is capable of achieving an amazing peak operating rate of 12.8 Gb per second. This solves the test bottleneck while allowing the operator to program the latest data just in time, all while attaining a very low programming cost per device.