Infineon(Siemens) XDPE132G5H QFN(56) Device
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IMPORTANT:
| Device Type: | Infineon Digital Multi-phase Controller |
| Device Memory Type: | Configuration Registers |
| Algorithm Programming Method: | PMBus |
| Supported Data File Format: | Multiple Image Configuration File (.mic) |
| Serialization Supported: | No |
Memory Organization:
| Memory Type |
Attributes(*) |
Included in Default Range (Y/N) | DUT PhysicalByte Address (hex) | BPWin BufferByte Address (hex) |
| Configuration Registers | R/W/E | Yes | 0000 – 0BFF | Determined by data file |
| Default Algorithm Range | — | — | 0000 – 0BFF | Determined by data file |
* R/W/E: readable and rewritable if not locked. Special Device Considerations:
| 1. | The CNFG section is limited to five image writes. If there are no more write attempts the CNFG section will not re-program correctly. |
| 2. | The User section is limited to 25 image writes. This algorithm will program the User image number as specified in the data file. |
| 3. | This algorithm will only attempt to verify the last User image in the data file by image number. |
| 4. | The CNFG section should be programmed at least once. Otherwise the User section may not verify correctly. |
| 5. | This algorithm will only program and verify the register ranges listed in the Configuration Register Mapping table above. The masks in the data file will determine which bits to verify. |
| 6. | Operations on the TRIM section are not supported. |
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Note: Lead Time is working days (5 days per week)
Adapters for Automated Programmers
| 9th Gen |
| FVE4ASMR56QFNA |
Adapters for Manual Programmers
| 9th Gen |
| FVE4ASMR56QFNA |
Adapters for Engineering Programmers
Last Updated: 05/18/2023
Additional information
| 8-bit Bytes | 1048576 |
|---|---|
| Manufacturer | Infineon(Siemens) |
| Packages | QFN(56) |
| Part Number | XDPE132G5H |
| Vcc(program) | 3.3 |
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