Infineon(Siemens) S25FL128SAGMFIG03 SOIC(16) Device

IMPORTANT: 128M-bit Serial Flash. This algorithm uses Standard SPI mode to Program and Verify/Read the device. The status register bits can be set under Device Config > Configure . Erase must be selected if device to be programmed already has QE bit enabled. The TBPARM OTP bit will be programmed first. You may not mix a top boot device with a bottom boot device. The default Device Range is set to [0000000h-0FFFFFFh]. Please modify the range under Device Config > Range if any of the Security Registers need to be included. The correct password value located in the range [1000400h-1000407h] may be read only after it is programmed and before the Password Mode has been selected by programming the Password Protection Mode bit to 0 in the ASP Register (ASP[2]). The OTP region is located in the range [1000020h-10003FFh]. The Factory Programmed 128-bit random number located at the beginning of the OTP region cannot be programmed and data in this region will not be shown in the Buffer Editor. OTP Lock bits are located in the Buffer location [1000010h-1000013h] and Reserved bits are located at [1000014h-100001Fh]. The device lock bits may be programmed under Device Congig > Configure. Each Group is devided into 64K Bytes of data. Boot sectors may only be locked in groups of 64K Bytes; thus these sectors will make up 2 bits in a group (First two bits for bottom boot devices and Last two bits for top boot devices.)